Real Chip Design and Verification Using Verilog and VHDL
Availability: In stock
Regular Price
AED 300.00
Special Price
AED 285.00
Real Chip Design and Verification Using Verilog and VHDL addresses the practical and real aspects of logic design, processes, and verification. It incorporates a collection of FPGA and ASIC design practices, and uses Verilog and VHDL as a tool for expression of the desired architectures. This book is not intended to teach either HDL, as there are several books specifically geared toward teaching the languages. However, it provides various architectural design primitives, applications, and verification techniques, along with design methodologies and common practices.
| Publisher Name | Createspace Independent Publishing Platform |
|---|---|
| Author Name | Hagendorf, Col |
| Format | Audio |
| Bisac Subject Major | TEC |
| Language | NG |
| Isbn 10 | 1539769712 |
| Isbn 13 | 9781539769712 |
| Target Age Group | min:NA, max:NA |
| Dimensions | 01.10" H x 00.08" L x 50.00" W |
| Page Count | 426 |
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