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An Introduction to Logic Circuit Testing
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An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips.
Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References
Publisher Name | Morgan & Claypool |
---|---|
Author Name | Hagendorf, Col |
Format | Audio |
Bisac Subject Major | COM |
Language | NG |
Isbn 10 | 1598293508 |
Isbn 13 | 9781598293500 |
Target Age Group | min:NA, max:NA |
Series | 000338804 |
Dimensions | 00.92" H x 50.07" L x 50.00" W |
Page Count | 112 |
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