Power-Constrained Testing of VLSI Circuits A Guide to the IEEE 1149.4 Test Standard
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AED 800.00
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This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
| Publisher Name | Springer |
|---|---|
| Author Name | Hagendorf, Col |
| Format | Audio |
| Bisac Subject Major | COM |
| Language | NG |
| Isbn 10 | 1441953159 |
| Isbn 13 | 9781441953155 |
| Target Age Group | min:NA, max:NA |
| Series | 00005637322B |
| Dimensions | 00.92" H x 10.06" L x 14.00" W |
| Page Count | 178 |
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